ð 0000:00:15.0:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:15.1:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:15.2:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:15.3:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:15.4:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:15.5:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:15.6:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:15.7:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:16.0:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:16.1:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:16.2:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:16.3:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:16.4:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:16.5:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:16.6:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:16.7:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:17.0:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:17.1:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:17.2:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:17.3:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:17.4:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:17.5:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:17.6:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:17.7:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:18.0:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:18.1:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:18.2:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:18.3:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:18.4:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:18.5:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:18.6:pcie004
|
-- |
drwxr-xr-x |
|
ð 0000:00:18.7:pcie004
|
-- |
drwxr-xr-x |
|
ð bind
|
4K |
--w------- |
|
ð uevent
|
4K |
--w------- |
|
ð unbind
|
4K |
--w------- |
|